CMOS related questions..

[sp3]

Hi all,

Anyone of you please answer the following questions :

1. How do we size the PMOS and NMOS transistors to increase the threshold voltage ?

2. Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate
later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?

Thanks,
sp3