Re: CMOS noise model.
Most fets have processing "problems". Problems involve things like crystaline structure defects at interfaces. These defects cause traps, where carriers can be "hung up" for a while, and released randomly in time, causing noise. Whenever you run such a device into saturation, where the fields are wildly changing at these interfaces, you end up with the most shot noise. So I would expect a cmos device to be much noisier in saturation.
As far as digital noise, yeah. If you are concerned about timing jitter on an OC-12 link, it is a big deal.