Cmos LNA Design Example in AWR
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I want to analyse with derivative superposition method cmos LNA in AWR. I try to simulate the circuit. But the results are very odd. I dont think they are solid results. But I dont know whats wrong about the circuit. I use 0.18um cmos process. I attached the images about my circuit and graphs (OIP3, S22,S11,S21, noise). Please help me about that. Thank you very much already.