CMOS inverter Question

[cimera7]

Heres an interview question which I am having trouble with:

Consider a CMOS inverter. Replace the NMOS in it with a PMOS. How would the VTC curve look like?

I was told that one PMOS would always be in saturation.

Since the source voltage of the lower PMOS is tied to Vout, how can we figure out if the lower PMOS is cutoff or not.

Help.

 

[sutapanaki]

This is equivalent to two PMOS in series which is as if you had a one PMOS with L=L1+L2. When input is 0, the lower PMOS is in saturation since Vg=Vd. As input continues to increase to Vdd, the lower PMOS remains in saturation. The output will most of the time follow the input with a certain offset. However, when input is close to Vdd (one threshold below Vdd) both transistors will be in cut-off and thus the output is floating with some uncontrolled leakage perhaps. Basically, this circuit is not an inverter.