Yes, agreed, the layout still contains polygons.
But, if you look at the FinFET layout (devices with interconnects), you can tell immediately it is not a planar CMOS technology.
The style is completely different.
To the contrary, if you look at planar technology layout, it's hard to tell if that is 90nm, or 65nm, or 40nm.
Also, the amount of efforts required to make a clean and good (electrically) layout in FinFET nodes is much more than that for planar CMOS technology layouts.