carrot
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Hi
In the below shown figures, First one is Top view and the second one is cross-sectional view.
In the cross-sectional view(second fig): for P-mos transistor -> in n-well region there is P+ for both source and drain, but near the drain region there is also n-well contact included. What is this? why is this included during CMOS Fabrication Technology> Is it purposely included? Is is acting like resistor?
Also in the Top View(first figure) it is showing, in n-well the pmos is connected to VDD. Is this right?
In the below shown figures, First one is Top view and the second one is cross-sectional view.
In the cross-sectional view(second fig): for P-mos transistor -> in n-well region there is P+ for both source and drain, but near the drain region there is also n-well contact included. What is this? why is this included during CMOS Fabrication Technology> Is it purposely included? Is is acting like resistor?
Also in the Top View(first figure) it is showing, in n-well the pmos is connected to VDD. Is this right?