cmos diff pair mismatch

[dsula]

transistor matching in analog cmos application

Hi,
I have an NMOS diff-pair that exhibits a certain offset. This offset is dependent on the input common mode. I have a hard time explaining this effect. Anybody knows? How can I avoid this? I don't care much about the offset of the diff pair, but I care about the offset not to change across a large common mode input range.

Or to give you some numbers. (The diff pair is used in a unity gain single ended miller op-amp)
I bias the inputs to 2V and I measure 5mV at the output.
I short the inputs to 3V and I measure 8mV at the output.

Thank you all for any thought on this.
ds

 

[pfd001]

it seems that there is a system offset in your amplifer

 

[pkalavakuru]

Let me know which technology ur using and whatz the dimensions for ur DIFF pair?

 

[nassim_el85]

Hi

you can find usefull information aboat the effect diff pair mismatch on offset at the old but usefull paper below:
Marcel J.M. Pelgrom, ...... "Transistor Matching in analog CMOS application"1998 IEEE,
also I know that offset is related to the input overdrive voltage and so on the CM one.

 

[tekno1]

Offset change with input common mode is due to (in order of most likely to less likely):

1) Input transistors back bias effecting the Vth so Delta-Vth contribution of offsett varies
2) Systematic offsett due to asymmetry
3) Impact ionization effect on some transistor with varying DC biases

 

[bsrivastava]

Choosing the larger dimension of diff pair may help in reducing offset values or use offset cancellation techniques.

hi tekno1,
Why are you referring back bias here? Is it not any finite value of Vsb (source to bulk) but it will be same for the both nmos diff pairs?

Also, what is impact ionization?

thanks
-Bharat

 

[jerryzhao]

Larher size input transistors. the detail size calculate reference the mismatch form from foundry.
ΔVth=A/√(W.L). where is coefficient u can get it from the mismatch form,

 

[MSSN]

can u post the schematic showing the amplifier and the feedback

 

[invent]

Maybe your transistors is not stable in saturation region, or you are using complementary differential input stage that is not properly tuned.

 

[okguy]

In the book of Razzavi "Design of analog CMOS IC", you have a very explanation on pages 463-480.

 

[niezimei]

a low PSRR will induce this situation either.

 

[shetoos_asu_65]

WELL...
according to my knowledge you have two solutions...
1)feedback to make the drain currents in the Nmos and Pmos the same because that missmatch will cause bad CMRR
2)the other solution is to decrease the common mode gain that will decrease the difference

i hope that i helped u
THANX