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CML comparator in 65nm CMOS - design rules

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tiportoolmo

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CML comparator

Hello everyone.

I need to design this circuit for a full flash ADC 4 GS/s in 65nm CMOS.
There are some rules to do that? for example, how can I choose W, I bias and Rload for this circuit?

please, I need a big help.

circuit:
 

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