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Closed feedback loops (I guess)

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leeloothedolphin

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Does anybody here know Abel? Well my questions is concerned about closed feedback loops. I have marked red my doubts. This code worked well while compiling with palasm. When we moved to lattice sw, errors started to appear in work, and they seem to be caused with closed feedback loop.

I'm now writing in vhdl and I know that when I write something like a <= a or b, i get an error from synthesis tool.
Well some people told me here that manufacturers recommended to use closed feedback loops in order to describe SR flip-flop, as here needed. Well I'm totally confused. Why this code isn't synthesizing good in Lattice, and in what occasions could we use closed feedback loops in HDL, and is this closed feedback loop at all. Please please help :(

"
MODULE D164IO


title 'Mach 192/96 za modul DMK164'
declarations
"VERZIJA 3
IA0 PIN 5;
IA1 PIN 6;
IA2 PIN 7;
IA3 PIN 8;
IA4 PIN 9;
IA5 PIN 10;
IA6 PIN 11;
IA7 PIN 12;
IA8 PIN 15;
IA9 PIN 16;
IA10 PIN 17;
IA11 PIN 18;


ISTB PIN 4;
IORES1 PIN 19;
INRES PIN 46;
IWT PIN 47;
ID0 PIN 3;

USPRO PIN 48;
USSIN PIN 53;
URSPER PIN 54;

C4MHZ PIN 49;

C4MHZ0 PIN 45 ;



ACK PIN 55 istype 'reg';
ACKDLY1 PIN 56 istype 'reg';
ACKDLY2 PIN 57 istype 'reg';
RD PIN 134 ;
WR PIN 133;
SEAD PIN 59;

RESET PIN 76;


C4MHZI PIN 131;
C2MHZ PIN 75 istype 'reg';
C1MHZ1 PIN 130 istype 'reg';
C1MHZ2 PIN 129;
FAILCTRL PIN 58 istype 'retain';

CS7 PIN 87;
CS8 PIN 86;

CS19 PIN 60;

USPROL1 PIN 114 istype 'reg';
USPROL2 PIN 113 istype 'reg';
USPROL3 PIN 112 istype 'reg';

RESCNPRO PIN 111;
LATCHPRO PIN 110;

Q0 PIN 66 istype 'reg';
Q1 PIN 67 istype 'reg';
Q2 PIN 68 istype 'reg';
Q3 PIN 69 istype 'reg';
Q4 PIN 70 istype 'reg';
Q5 PIN 71 istype 'reg';

C100KHZ PIN 72;

EQUATIONS

"CLOCK SIGNAL


ACK.CLK =C4MHZ;

ACKDLY1.CLK =C4MHZ;
ACKDLY2.CLK =C4MHZ;

C2MHZ.CLK =C4MHZ;

C1MHZ1.CLK =C4MHZ;

USPROL1.CLK =C4MHZ;
USPROL2.CLK =C4MHZ;
USPROL3.CLK =C4MHZ;

USSINL1.CLK =C4MHZ;
USSINL2.CLK =C4MHZ;
USSINL3.CLK =C4MHZ;

URSPERL1.CLK =C4MHZ;
URSPERL2.CLK =C4MHZ;
URSPERL3.CLK =C4MHZ;

Q0.CLK =C4MHZ;
Q1.CLK =C4MHZ;
Q2.CLK =C4MHZ;
Q3.CLK =C4MHZ;
Q4.CLK =C4MHZ;
Q5.CLK =C4MHZ;


ACK := !ACKDLY2 & RESET & !ISTB & !SEAD;
!ACKDLY1 := RESET & !ISTB & !SEAD;
!ACKDLY2 := !ACKDLY1;
!RD = !ACKDLY2 & !ISTB & !IWT & !SEAD;
!WR = !ACKDLY2 & !ISTB & IWT & !SEAD & !ACK;
!SEAD = !IA11 & IA10 & !IA9 & IA8 & !IA7 & !IA6;


!RESET = !IORES1 # !INRES;
!C4MHZI = C4MHZ0;
!C2MHZ := C2MHZ;
!C1MHZ1 := C1MHZ1 & C2MHZ # !C1MHZ1 & !C2MHZ;
C1MHZ2 = !C1MHZ1;
FAILCTRL = !RESET # CS7 & !ID0 # FAILCTRL & !(CS7 & ID0);

CS7 = !ACKDLY2 & !ISTB & IWT & !SEAD & !IA5 & IA4 & IA3 & !IA2 & !IA1 & !IA0 & !ACK;

!CS19 = !ACKDLY1 & !ISTB & IWT & IA5 & !IA4 & !IA3 & IA2;



USPROL1 := USPRO;
USPROL2 := USPROL1;
USPROL3 := USPROL2;

!LATCHPRO = USPROL1 & !USPROL2 # !USPROL1 & USPROL2;
!RESCNPRO = USPROL2 & !USPROL3 # !USPROL2 & USPROL3;

Q0 := !Q0 & C100KHZ;
Q1 := ( !Q1 & !Q0 # Q1 & Q0) & C100KHZ;
Q2 := ( !Q2 & !Q1 & !Q0 # Q2 & Q1 # Q2 & Q0) & C100KHZ;
Q3 := (!Q3 & !Q2 & !Q1 & !Q0 # Q3 & Q2 # Q3 &Q1 # Q3 &Q0 ) & C100KHZ;
Q4 := (!Q4 & !Q3 & !Q2 & !Q1 & !Q0 # Q4& Q3
# Q4 & Q2 # Q4 & Q1 # Q4 & Q0) & C100KHZ;
Q5 := (!Q5 & !Q4 & !Q3 & !Q2 & !Q1 & !Q0 # Q5 & Q4 # Q5
& Q3 # Q5 & Q2 # Q5 & Q1 # Q5 & Q0) & C100KHZ;

!C100KHZ = !Q5 & Q4 & Q3 & !Q2 & !Q1 & Q0;

END

"
 

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