If you do not use a clocking block, then you need to synchronize and provide skews as if your testbench was another piece of RTL connected to your DUT. This is easy to understand if you do both design and verification. For the engineer just doing verification, some of the idiosyncrasies of Verilog's wires versus variables semantics can be confusing. The clocking block abstracts some of that away from the testbench writer.
See my DVCon12 paper that discusses this: **broken link removed**