[SOLVED] Clock Tree Synthesis

[sharath666]

Hi friends,

Can someone tell me what is the motivation for the CTS tool to add buffers in the clock path in an ASIC during the CTS process?

Managing fanout is one reason I suppose. What are the other reasons?

 

[rca]

the goal of the CTS step is to reduce the skew, so some buffers are needed to drive the clock properly.

 

[artmalik]

The buffer insertion is done more than to reduce just the skew. The buffers are added to do time borrowing as well to improve the overall speed of the design. This is done using CCopt ( clock concurrent optimization) from Azuro/Cadence.
Basically you play with logic delay and clock skew to achieve better timing.

Also the other things are important like reducing the skew, buffering to drive longer wires, etc etc

 

[childs72]

The buffer insertion is done more than to reduce just the skew. The buffers are added to do time borrowing as well to improve the overall speed of the design. This is done using CCopt ( clock concurrent optimization) from Azuro/Cadence.
Basically you play with logic delay and clock skew to achieve better timing.

Also the other things are important like reducing the skew, buffering to drive longer wires, etc etc

Hi, I assume you mentioned 2 ways how CTS improve timing:
1. by play with skew, which also know as "beneficial skew" (this is used, at least by Altera's QII FPGA compiler)
2. "time borrowing" -> this is what I don't really understand. My previous understanding towards this term is related to timing path that involved latches. Do you mind to explain how time borrowing works in clock network? THanks!

 

[artmalik]

1) The beneficial skew is the useful skew....
2) As far as time borrowing is concerned..please read this paper
or you can google CCopt Azuro this company is part of Cadence....and does Clock Current Optimization there is a paper on this....