Re: Clock Tree Synthesis
Hai,
hope u know what is CTS.
Its just playing wit the inverters or buffers or dealy cells such that making all the flops in reaching the clock at same time.
Well regarding expertise, just managining to slove the issues and considering why is that issue coming into picture, what is requried for that, how to solve that.
before that u need to understand some of the issues like
What is clock tree, is that propagated or generated. if different clock domains are there y is that? what is acceptable skew, info of PLL
hope if u become familair in this u can become expertise in CTS or CTO