clock tree simulation
Do you really need to do a transistor level sim for power analysis? I would have thought you could just extract a post-route Verilog netlist from Astro and simulate that capturing a SAIF/TCF file, which you can then use for power analysis in DC.
Depends how accurate you want the result to be, I guess. If you do want to do a very accurate spice sim, I guess you will need an extraction tool such as STAR-RCXT to create the netlist to simulate.