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for most clock tree, it need small skew, small transition. but on the contrary, the physical tree do not need these. common physical trees are reset or high-fanout net. You can use tool's internal optimize engine to route high fanout net. But for clock, it must use clock tree synthesis(CTS) to generate clock tree. Synopsys Physical Compiler have the ability of design physical tree. You can refer the doc.
Good luck
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