clock tree building in synthesis

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jaya sree

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hai ,
will clock be built in synthesis ( pre pnr stage)

during cts stage in pnr , i am seeing tool is deleting many preexistinng clock buffers and inverters) . does that mean clock was built during synthesis ?
 

The first phase of a cts is to removed every buffers and inverter, only mux and gate elements are preserved.
In the second phase, the clock tree is realize.
During the synthesis, only some gated-latch could be added.
 
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o.k . but when did tool insert these buffers and inverters ? before pnr ?
 

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