flyjuju2
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Hello everybody !
I have a project to realize, i.e. the connection of many FPGA (board Altera APEX 20KE) into a Network-on-Chip. The main issue I have is that the has a frequency of 33.333MHz with a precision of +- 1ppm.
So, when I send informations (serially) between 2 FPGA, I have absolutely no guarantee about the synchronisation of the clocks of the 2 boards, and so on the data that my 2nd fpga reads. The main idea is so to propagate the clock from the 1st fpga to all others via the only wire, that is to say the data line. For this, I think about using a manchester encoding+PLL.
The problem is that the only PLL available on APEX board is "altclklock", i.e. just a multiplication/division of the inital clock frequency.
My question is the following :
-is there any way to create a "real" digital PLL in VHDL ?
-is there any other ways to transmit serially the clock ?
Thansk a lot for your help !!!
I have a project to realize, i.e. the connection of many FPGA (board Altera APEX 20KE) into a Network-on-Chip. The main issue I have is that the has a frequency of 33.333MHz with a precision of +- 1ppm.
So, when I send informations (serially) between 2 FPGA, I have absolutely no guarantee about the synchronisation of the clocks of the 2 boards, and so on the data that my 2nd fpga reads. The main idea is so to propagate the clock from the 1st fpga to all others via the only wire, that is to say the data line. For this, I think about using a manchester encoding+PLL.
The problem is that the only PLL available on APEX board is "altclklock", i.e. just a multiplication/division of the inital clock frequency.
My question is the following :
-is there any way to create a "real" digital PLL in VHDL ?
-is there any other ways to transmit serially the clock ?
Thansk a lot for your help !!!
