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Clock Transition constraint v/s Data transition constraint

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eda_rattle

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Hi All,

What are the reasons for keeping the max_transition at clock nets higher than data nets ?
Only due to Xtalk ? Or there are other reasons also.
For eg, in postcts stage if you have :

set_max_transition 1.0 -clock_path [get_clocks X_CLK]
set_max_transition 1.2 [get_designs *]

Thanks & Regards,
eda_rattle
 

no reason. better clock tree?
 

Then why clock is kept at higher transition & not data ?
 

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