NikosTS
Advanced Member level 4
Clock to Q (Flip Flop) delay missmatch between analog and digital simulators
Hello everyone,
I have a problem when simulating a single DFF, regarding the clock to Q( FF's output) delay.
When importing an instance of a DFF on Cadence Virtuoso and use transient analysis with a testebench that simply produces pulses as an input to the flip flop, I get around 140 ps of delay between the clock's rising edge and the change at the outpin pin ( Q ).
On the other hand, when i synthesize a DFF on Cadence RTL Compiler and then use NCLaunch to simulate it ( annotating the .sdf file produced by RTL Compiler ) I get a delay of 232 ps.
The same cell i use as an instance on Virtuoso is also produced from the synthesis procedure. Also, the operating conditions are typical on both cases.
Anyone has any idea as to why this would happen?
If i didnt make something clear, please tell me.
Thank you in advance,
Nikos
Hello everyone,
I have a problem when simulating a single DFF, regarding the clock to Q( FF's output) delay.
When importing an instance of a DFF on Cadence Virtuoso and use transient analysis with a testebench that simply produces pulses as an input to the flip flop, I get around 140 ps of delay between the clock's rising edge and the change at the outpin pin ( Q ).
On the other hand, when i synthesize a DFF on Cadence RTL Compiler and then use NCLaunch to simulate it ( annotating the .sdf file produced by RTL Compiler ) I get a delay of 232 ps.
The same cell i use as an instance on Virtuoso is also produced from the synthesis procedure. Also, the operating conditions are typical on both cases.
Anyone has any idea as to why this would happen?
If i didnt make something clear, please tell me.
Thank you in advance,
Nikos