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Clock skew constraints for clock tree synthesis

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yuhiub90

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Hi guys,

I'm wondering whether or not to constrain the clock skew (uncertainty) for placement and clock tree synthesis.
Does this affect the clock path during optimization process when building clock tree, e.g. buffers are added to clock path to satisfy the constrained skew. Or it's just optimization on data path to satisfy setup/hold requirements with the constrained clock skew?

Please give me some advices.
Thanks.
 

raj1435

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Hi,

Uncertainty will be help full to satisfy the setup and Hold requirements. Inserting the buffers on the design will be the way to fix the setup or hold violations. Tool will take care the best approach is to insert the buffer or to reduce the data path delay.
 

yuhiub90

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I know it. But how optimization is done. Does the synthesizer try to build the clock tree with the constrained skew. Or it still perform zero skew optimization, the specified uncertainty margins (setup/hold skew) is used to prevent skew due to variabilities when real chip is fab. Which one is better, constrain or non-constrain it?

Thanks
 

hoanglongroyal

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hi Yuhiub90,
as I'm using uncertainty in synthesizing, it's just used as a margin which you want to reserve for Back-End later.
in my case, synthesizer do not build clock tree follow the uncertainty and clock-tree timing is idea.
I put a short report timing to you bellow:
Code:
Point                                       Fanout       Cap     Trans      Incr       Path
  ----------------------------------------------------------------------------------------------
  clock clk_core (rise edge)                                                  0.00       0.00
  [B]clock network delay (ideal)[/B]                                                 0.00       0.00
.
.
.
  clock clk_core (rise edge)                                                1.125      1.125
  clock network delay (ideal)                                                0.000      1.125
 [B] inter-clock uncertainty                                                   -0.250      0.875[/B]
  output external delay                                                     -0.837      0.038
  data required time                                                                    0.038
  ----------------------------------------------------------------------------------------------
  data required time                                                                    0.038
  data arrival time                                                                    -0.091
  ----------------------------------------------------------------------------------------------
  slack (VIOLATED)                                                                     -0.053
you can see the uncertainty in example make slack more pessimism.
totally, as I know, uncertainty is used for model clk skew, jitter, ... as margin for design.

- - - Updated - - -

Which one is better, constrain or non-constrain it?
I forgot this thing, if you have right uncertainty, then you're good to meet your timing goal.
- you put an enough uncertainty, can help synthesis tool follow and optimize more in your design.
- if you do not specify uncertainty, maybe your design is met as 0 margin, and synthesis tool do not need to optimize --> back-end guy will kill you if their work become more complex.
- if you specify uncertainty too big, synthesis tool will give up because of impossible optimization.
 

yuhiub90

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thanks hoanglongroyal,

Your report doesn't show clock skew because you are considering ideal clock network. You can see it when invoking set_propagated_clock and back-annotated the delay information from SDF file.
I got the idea of using uncertainty margin for logic synthesis, it's for timing analysis when clock tree has not been implemented. But for back-end stage, is this constraints necessary?
 

hoanglongroyal

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thanks hoanglongroyal,

Your report doesn't show clock skew because you are considering ideal clock network. You can see it when invoking set_propagated_clock and back-annotated the delay information from SDF file.
I got the idea of using uncertainty margin for logic synthesis, it's for timing analysis when clock tree has not been implemented. But for back-end stage, is this constraints necessary?
hi yuhiub90,
as I mention, uncertainty is margin/budget timing for your design, it models skew,jitter,... timing tool will make report more pessimism by uncertainty. and this is what we need to safe design. you can't make sure 100% that the skew is the same at any time, any where, as your chip come real because of variation (by temperature, fab fault,...). I mean , always have variant value that you need to cover in skew, uncertainty.
of course in some case, back-end guy can reduce skew uncertainty at some paths, such as paths short clock tree, or some paths which they can make sure less variation.
 
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