Clock skew is the maximam difference of the delay time from the clock source to all the clock port of the flip-flops in that clock domain. And Clock delay, in this sense, is the average(mean) of the above delays.
PLL is for phase lock loop. In the sense of clock synthesizer, it contains a VCO(valtage control Oscilliator), generating output clock with a frequency M/N of the input reference clock, and the feedback loop that ensures the M/N relationship and the stability.
DLL is for Delay lock loop, instead of VCO, it contains only Delay array, that can only adjust the delay(phase), from the input reference clock, and sometimes, capable of generating 2X clock(Xilinx DCM).