Source pins of clock trees in the fanout of another clock
For example, in Figure(which i have posted earlier) the source pin of the driven clock (clk2) is an ignore pin of the driving clock (clk1). Sinks of the driven clock are not considered sinks of the driving clock.
This is the context given in books.According to this, clk1 is driving clk and clk2 is driven clk.
i got your point. But if we assume, clk1 is master clock and clk2 is generated clock. then sink pins for clk2 would be Flip flop shown in picture, but what would be the sink pin for master clock (clk1 in this case)?
yes, but i forgot to mention that both upper flop and down flop are driven by clk2. Then, the clk divider (which we are assuming virtually for generating clk2) is the sink pin or not?
basically i am trying to clear my concept related to sink pin and ignore pins.