Clock Signal,burying between Pwr & Gnd Planes

[Rame]

Hi,

In one of an Emc article from Henry Otts,it says that you need to bury the clock signals between Power and gnd plane whenever possible...

I have studied in several article saying to place the Clk signal(top layer) close to the ground plane for emi/emc issues,but then the above statement, what i saw in the article was new to me,can someone from the forum shed some light.


Suggestions,views and insights would be greatly appreciated.


Regards

Ramesh

 

[deh_fuhrer]

It is related to substrate coupling.Toggling of the clock always introduce some noise in the substrate and if you place clock near the gnd then substrate noise will effect it more than the power(take it a simple way if you place clock b/w power and gnd the noise gets cancelled).Lets say noise introduce a 0.001V increase in gnd then it also introduce same shift in Power also.So the threshold of the mos device is less affected.

 

[Rame]

Hi,

Can you send across article, which explains in detail about the topic in the subject line,i presume the layer stackup should be more than the 4 layers,also can you tell me which is the ideal layer stackup!!!.

Regards

Ramesh

 

[touringmike]

A lot will depend upon the amount of layers your board contains.

On a 4 layer board, It's best to keep the CLK signal on the originating layer (say the top layer), away from all other signals, and routed without vias. PWR and GND would ideally be the internal layers. A GND shield around the CLK signal will shield any possible noise from other signal traces. The GND shield can have vias to the plane layer at any given point.

On an 8 layer or more layout, a via into an internal trace layer at the origin and termination point with the trace staying on the internal layer without vias to any other layer is preferred. PWR and GND layers would sandwich the internal trace layer. Again, all other signal traces should be kept away from the CLK signal.

 

[verg]

As touringmike said, it is ideal for clock lines to be on originating layers and the rule is that, the spacing of the clock lines should be at least 3 times the clock signal trace width....and also be ideal if these signals are sorounded by ground traces....(PWR or GND does'nt make any difference)...

 

[buenos]

i putted clock signals onto inner layers, between 2 GND planes. and other signals are far away: d>5h

because i wanted to prevent:
-noise coupling from clock to other circuits, like WLAN card, few milimeters above the motherboard. sensitive RF circuits.
-noise coupling to clock: this way i can protect it against generating jitter. for some clocks, jitter is very critical, like in my design, a 33MHz reference clock, which is multiplied by a PLL to produce 200MHz DDR memory clock.

did i wrong?

is the article on the internet?

 

[verg]

Having the clock signals along the plane layers is another ideal thing to do as long as these signals are not getting in parallel to the signals on the adjacent layer. Rule of the thumb is "these signals should always be routed 90 degrees against the direction of the signals on the adjacent layer". Now if this is not possible, they
can run in parallel with the signals of the adjacent layer, as long as they should be
along short lengths at a time...Hopefullly you know what I meant, and only if you can't do the first. Also, refrain from routing clock lines under power supply circuitry...Cheers

 

[chinta]

Also make sure that the copper on the ground layer does not have any slots under these routed clock traces

 

[avesat]

Hi,

Can you send across article, which explains in detail about the topic in the subject line,i presume the layer stackup should be more than the 4 layers,also can you tell me which is the ideal layer stackup!!!.

Regards

Ramesh

Try to read this:
HIGH-SPEED DIGITAL DESIGN. Howard W. Johnson, Martin Graham
Chapter 5 "Ground Planes and Layer Stacking"

Best Regards!

Added after 28 minutes:

i putted clock signals onto inner layers, between 2 GND planes. and other signals are far away: d>5h

because i wanted to prevent:
-noise coupling from clock to other circuits, like WLAN card, few milimeters above the motherboard. sensitive RF circuits.
-noise coupling to clock: this way i can protect it against generating jitter. for some clocks, jitter is very critical, like in my design, a 33MHz reference clock, which is multiplied by a PLL to produce 200MHz DDR memory clock.

did i wrong?

is the article on the internet?

Try to look in this books:

PH-Signal_Integrity_Simplified-Eric_Bogatin
PH-Signal_Integrity_Issues_and_Printed_Circuit_Board_Design-Douglas_Brooks
Artech House - High Speed Circuit Board Signal Integrity - Stephen Thierauf