Clock problem (virtex-7)

[spman]

Hi,
I have bought a Virtex-7 board. The board has a 100MHz Silicon Labs programmable clock (570FBC000642DG). The problem is that I can't use this clock. I used an IBUFGDS in this manner:

input clk_p, clk_n;	
wire clk;

IBUFGDS clkbuf (.I(clk_p), .IB(clk_n), .O(clk));

and ucf:

NET "clk_p" IOSTANDARD = LVDS;
NET "clk_n" IOSTANDARD = LVDS;
NET "clk_p" LOC = AU20;
NET "clk_n" LOC = AV19;

I'm sure about location constraints but not about IOSTANDARDS.
The design is implemented without any warnings. But the clock signal doesn't work!

Please help me. Thanks in advance

 

[ads-ee]

Does the V7 board have external differential termination on the clock? If no then you'll need to enable the on-die termination. It's something like DIFF_TERM=TRUE. Look up the exact UCF syntax.

You can also check if the OE pin of the SiLab part is high to make sure it's output is enabled.

 

[imbichie]

Which tool you are using?
Is it Xilinx or Vivado?
I think it should be vivado, if its vivado, you should use the *.xdc file instead of *.ucf file.
If you are using the *.xdc file, then the constraints are different,
NET constraints are using in *.ucf file, but in *.xdc file you should use

set_property PACKAGE_PIN AU20 [get_ports clk_p]
set_property PACKAGE_PIN AV19 [get_ports clk_n]
set_property IOSTANDARD LVDS [get_ports clk_p]
set_property IOSTANDARD LVDS [get_ports clk_n]

 

[ads-ee]

Still need to add the set_property DIFF_TERM for the clock pins.