clock network power - prime time px

[Thawra-Kadeed]

I have a question please related to the internal power produced by clock network.

I am trying to apply 0 traffic to my design to see how much switching power would consume, which should be so small.
Here in this case I have this results:

Power Group Power Power Power Power ( %) Attrs
--------------------------------------------------------------------------------
clock_network 0.0419 0.0000 0.0000 0.0419 (99.78%) i
register 6.335e-06 4.843e-06 1.968e-05 3.086e-05 ( 0.07%)
combinational 1.356e-05 1.677e-05 3.015e-05 6.048e-05 ( 0.14%)
sequential 7.147e-10 7.233e-10 4.124e-08 4.268e-08 ( 0.00%)
memory 0.0000 0.0000 0.0000 0.0000 ( 0.00%)
io_pad 0.0000 0.0000 0.0000 0.0000 ( 0.00%)
black_box 0.0000 0.0000 0.0000 0.0000 ( 0.00%)

Net Switching Power = 2.161e-05 ( 0.05%)
Cell Internal Power = 0.0419 (99.83%)
Cell Leakage Power = 4.988e-05 ( 0.12%)
---------
Total Power = 0.0419 (100.00%)


And here we see obviously that the internal power is too big because of the internal power of clock network which is not important for me since I have no traffic in the input.
So I used this command: "set power_clock_network_include_register_clock_pin_power false" to get rid from this high Int power value but afterward actually I still have the same value as following:

Internal Switching Leakage Total
Power Group Power Power Power Power ( %) Attrs
--------------------------------------------------------------------------------
clock_network 0.0000 0.0000 0.0000 0.0000 ( 0.00%)
register 0.0419 4.843e-06 1.968e-05 0.0419 (99.86%) i
combinational 1.356e-05 1.677e-05 3.015e-05 6.048e-05 ( 0.14%)
sequential 7.147e-10 7.233e-10 4.124e-08 4.268e-08 ( 0.00%)

And it's clear that the tool moves the value to registers clock internal power. Does any ine have an idea how can I disable the register clock internal power from the output reported power?

Thanks

 

[ThisIsNotSam]

what you are trying to achieve exactly? whatever you are doing, you are not stopping the clock from ticking. that is where your power is coming from.

 

[Thawra-Kadeed]

Thanks for your participation.
I am trying to inject 2 diff. traffic to my design to estimate the switching power. I had good results where the switching power increases every time I load more data.

But the thing is I was surprised a bit that the internal power is a bit high and then I discovered that it comes from the clock network. So I tried to stop the clock network power when I have 0 traffic where propagation the clock here into registers doesn't make any sense.

Sorry, are you sure that we can't tell the tool to don't calculate the clock network power during the power estimation where we don't have real inputs?

This idea is very important for me because I need the tool to report the power without taking into consider the clock network power.

Thanks

 

[ThisIsNotSam]

This whole thread makes no sense. I don't know why you would be surprised. It's a clock network, it is supposed to be on all the time (except if you have power gating, but let's not go there). Are you sure you understand how a clock tree works? Just because the D input of all flops is fixed (what you call "no traffic"), it doesn't stop the clock tree from working.

"Sorry, are you sure that we can't tell the tool to don't calculate the clock network power during the power estimation where we don't have real inputs?"
Why can't you just filter the dynamic power and get the number that you want? It's a simple subtraction problem.
total_P = clock_P + logic_cells_P;

 

[Thawra-Kadeed]

Dear ThisIsNotSam, thnks for your attention.
I know that if we have no inputs that doesn't mean we have no clock tree. For that I tried to search turning off the clk tree since there is no need to keep the circuit works and consume power where we don't have inputs.

But any way, I can simply ignore of filter the clock power from the power report. But what made me surprised is that the internal power which I have at the output which coming from the clock network power is too big:

Power Group             Internal  Power   
----------------------------------------------------
clock_network              0.0419   
register                      1.023e-04 
combinational             1.692e-04 
sequential                  8.916e-07

As you see from above table, this is maybe because I use ram comprised from many registers where the clock tree here doing a lot and produce such a big internal power.

 

[ThisIsNotSam]

It is not surprising, you are comparing dynamic power to static power, essentially.