Clock Multiplier using Combinational Logic

[dinesh.4126]

Hi,
Can somebody give some hint how to design clock multiplier(double the frequency) using combinational logic.

 

[FvM]

Basically, an XOR gate with one input delayed can achieve this. You have to check, if it's feasible with your available logic.

 

[vlsi_freak]

If you are using FPGA, use clock managers, DCM available inside the FPGA.
Dont make custom clock gating, clock multipliers in FPGA as it may cause clock glitching.

regards,
freak