Jan 4, 2010 #1 D dinesh.4126 Member level 5 Joined Feb 27, 2008 Messages 83 Helped 1 Reputation 2 Reaction score 1 Trophy points 1,288 Activity points 1,841 Hi, Can somebody give some hint how to design clock multiplier(double the frequency) using combinational logic.
Hi, Can somebody give some hint how to design clock multiplier(double the frequency) using combinational logic.
Jan 4, 2010 #2 FvM Super Moderator Staff member Joined Jan 22, 2008 Messages 52,513 Helped 14,758 Reputation 29,798 Reaction score 14,128 Trophy points 1,393 Location Bochum, Germany Activity points 298,482 Basically, an XOR gate with one input delayed can achieve this. You have to check, if it's feasible with your available logic.
Basically, an XOR gate with one input delayed can achieve this. You have to check, if it's feasible with your available logic.
Jan 10, 2010 #3 V vlsi_freak Full Member level 2 Joined Sep 3, 2007 Messages 127 Helped 14 Reputation 28 Reaction score 8 Trophy points 1,298 Activity points 2,041 If you are using FPGA, use clock managers, DCM available inside the FPGA. Dont make custom clock gating, clock multipliers in FPGA as it may cause clock glitching. regards, freak
If you are using FPGA, use clock managers, DCM available inside the FPGA. Dont make custom clock gating, clock multipliers in FPGA as it may cause clock glitching. regards, freak