If you can live with the added jitter you can always try the built in clocking functions/capabilities of the device you are using..i.e. DCM in a Xilinx part.
for the clock of 1/4 of the original frequency, just make a clock divider....a circuit that counts every 4 clock cycles of the original clock and generates 1 pulse of clock...
for the multiplication, there is no way to design a clock multiplier in VHDL....so you'll have to use a PLL or a DCM (Digital Clock Manager)...depending on your board...
use PLL, because output of PLL is connected to the global clock routing. When using counter for the clock dividing output in most FPGA is not connected to clock routing, in this case seting up timing constrains become unpredictable
In a modern Xilinx FPGA, you can connect a counter's output signal to a low-skew global clock net by simply inserting a clock buffer primitive such as BUFG. You won't have much control over the buffer's propagation delay, but that's fine for some applications.