Hi sixth,
Let me try to explain accumulating jitter in time domain by a simple example.
Let's consider a clock source with frequency 1 GHz (time period = 1 ns).
Let us also consider that due to some fixed offset, the source has jitter which alternates as +1 ps and -0.5 ps consecutively - ie, the first transition occurs at 0 second, second transition occurs at 1.001 ns (instead of 1 ns) and the third at 2.0005 ns (instead of 2 ns). Due to accumulating or phase jitter, the clock has advanced by 0.5 ps in time or in other words, the clock accumulates 0.5 ps every 2 cycles if we have alterating + 1ps and -0.5 ps of jitter sequence.
By working this over consecutive cycles, you can convince yourself that the clock would have advanced a full cycle (1 ns) after 2000 cycles, ie, the clock misses one cycle after 2000 cycles. If the ideal clock has 2000 cycles (2000 rising and falling edges), the jittered clock due to accumulating/phase jitter will have only 1999 cycles (1999 rising and falling edges).
Thus accumulating jitter will miss cycles over a large period of time. and the number of cycles depends on the polarity and value of jitter (early (negative) or late (positive)), which implies that the clock may miss cycles or may have an extra cycle. In our example, if the jitter sequence is -1 ps and + 0.5 ps, the jittered clock will have 2001 cycles when the ideal clock has 2000 cycles.
I hope this explanation is clear.
Bharath