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# Clock jitter effect on sampling system

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#### sixth

##### Member level 4
As all know, clock jitter has important effect to the sampling system and can decrease the sytem performance greatly. But is there a limit about the performance descend?
For the sample and hod circuit, the SNR due to clock jitter can be expressed as SNR=-20*log(2*pi*Fin*deltat),where deltat is the variation of the clock jitter. I dont know if the the deltat is cycle-to-cycle jitter or a T-cycle jitter(accumulated jitter). For a PLL or a crystal, the cycle-to-cycle jitter will be accumulated without a limit. Then it seems we can draw a conclusion that the system performance will inevitably decrease to zero due to the accumulated jitter. Is this right?

sixth

Hi,

the delta in that formula is the RMS jitter variaion or standard deviation of the variation of clock period. By accumulated jitter, are you meaning frequency drift? Anyhow, maybe this link might be helpful:

Regards,
TS

tiger_shark said:
Hi,

the delta in that formula is the RMS jitter variaion or standard deviation of the variation of clock period. By accumulated jitter, are you meaning frequency drift? Anyhow, maybe this link might be helpful:

h**p://www.edn.com/article/ca484488.html

Regards,
TS
Thank you, tiger.
https://www.designers-guide.org/Analysis/PLLjitter.pdf
As Kundert had said, "Accumulating jitter is characterized by an undesired variation in the time since the previous output transition, thus the uncertainty of when a transition occurs accumulates with every transition. Compared with a jitter free signal, the frequency of a signal exhibiting accumulating jitter fluctuates randomly, and the phase drifts without bound." So, the accumulate jitter is phase drift, not a frequency drift.
For example, for a 1MHz sine wave, we use a 4MHz clock signal to sample it. For a ideal clock, the sample point will be at the same position in every cycle. But for a clock with accumulate jitter, if the time is long enough, will the sample point spread all cycle of the sine wave? And will it decrease the SNR to zero? I can understand this problem in frequency domain, but I can't understand it in time domain.

sixth

sixth said:
Thank you, tiger.
h**p://www.designers-guide.org/Analysis/PLLjitter.pdf
As Kundert had said, "Accumulating jitter is characterized by an undesired variation in the time since the previous output transition, thus the uncertainty of when a transition occurs accumulates with every transition. Compared with a jitter free signal, the frequency of a signal exhibiting accumulating jitter fluctuates randomly, and the phase drifts without bound." So, the accumulate jitter is phase drift, not a frequency drift.
For example, for a 1MHz sine wave, we use a 4MHz clock signal to sample it. For a ideal clock, the sample point will be at the same position in every cycle. But for a clock with accumulate jitter, if the time is long enough, will the sample point spread all cycle of the sine wave? And will it decrease the SNR to zero? I can understand this problem in frequency domain, but I can't understand it in time domain.

sixth

Hi sixth,
Let me try to explain accumulating jitter in time domain by a simple example.
Let's consider a clock source with frequency 1 GHz (time period = 1 ns).
Let us also consider that due to some fixed offset, the source has jitter which alternates as +1 ps and -0.5 ps consecutively - ie, the first transition occurs at 0 second, second transition occurs at 1.001 ns (instead of 1 ns) and the third at 2.0005 ns (instead of 2 ns). Due to accumulating or phase jitter, the clock has advanced by 0.5 ps in time or in other words, the clock accumulates 0.5 ps every 2 cycles if we have alterating + 1ps and -0.5 ps of jitter sequence.
By working this over consecutive cycles, you can convince yourself that the clock would have advanced a full cycle (1 ns) after 2000 cycles, ie, the clock misses one cycle after 2000 cycles. If the ideal clock has 2000 cycles (2000 rising and falling edges), the jittered clock due to accumulating/phase jitter will have only 1999 cycles (1999 rising and falling edges).
Thus accumulating jitter will miss cycles over a large period of time. and the number of cycles depends on the polarity and value of jitter (early (negative) or late (positive)), which implies that the clock may miss cycles or may have an extra cycle. In our example, if the jitter sequence is -1 ps and + 0.5 ps, the jittered clock will have 2001 cycles when the ideal clock has 2000 cycles.
I hope this explanation is clear.

Bharath

Hi sixth,
Let me try to explain accumulating jitter in time domain by a simple example.
Let's consider a clock source with frequency 1 GHz (time period = 1 ns).
Let us also consider that due to some fixed offset, the source has jitter which alternates as +1 ps and -0.5 ps consecutively - ie, the first transition occurs at 0 second, second transition occurs at 1.001 ns (instead of 1 ns) and the third at 2.0005 ns (instead of 2 ns). Due to accumulating or phase jitter, the clock has advanced by 0.5 ps in time or in other words, the clock accumulates 0.5 ps every 2 cycles if we have alterating + 1ps and -0.5 ps of jitter sequence.
By working this over consecutive cycles, you can convince yourself that the clock would have advanced a full cycle (1 ns) after 2000 cycles, ie, the clock misses one cycle after 2000 cycles. If the ideal clock has 2000 cycles (2000 rising and falling edges), the jittered clock due to accumulating/phase jitter will have only 1999 cycles (1999 rising and falling edges).
Thus accumulating jitter will miss cycles over a large period of time. and the number of cycles depends on the polarity and value of jitter (early (negative) or late (positive)), which implies that the clock may miss cycles or may have an extra cycle. In our example, if the jitter sequence is -1 ps and + 0.5 ps, the jittered clock will have 2001 cycles when the ideal clock has 2000 cycles.
I hope this explanation is clear.

Bharath
Hi, Bharath
Thanks for your explanation. It is very clear.
My question is if this kind of accumulate jitter will affect the performance of the sampling system or not? My simulation shows that the SNR of a sampling system with accumulate jitter is lower than the case without accumulate jitter. Is this reasonable?
From time domain, if we looking at the eyediagram of the sample-and-hold waveform, with the increasing of time, the eyediagram will close finally. Does this situation means that the SNR of the sampling system has dropped to zero?

sixth

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