implement two clock edges
The "50 MHz" in line 2 does not affect the counting behavior. It is a Xilinx ISE synthesis timing constraint that tells the synthesizer to route the design so it works reliably up to 50 MHz. You should change this value to your input clock frequency. (This constraint is unnecessary if you have already specified it elsewhere in your ISE project.)
The "50000000" in line 7 controls the counting behavior. You should change this value according to your desired frequency division ratio. For example, if your clock is 2 MHz, and your desired output frequency is 20 Hz, then you should change 50000000 to 2000000/20 (or 100000). It would also be a good idea to change the bit width of the "count" register accordingly.
I don't understand your sentence about two clock edges, 10 seconds, and 20 clock edges. Sorry.
If you need help with your code, it's better to upload it here (perhaps as a ZIP attachment) instead of email, so other people can help you too.