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clock grouping in SOC encounter?

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vlsitechnology

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Can anyone explain me the that how can we use clock grouping technique in SOC encounter to optimize the design??
 

Clock grouping is setting a group of leaf cells as a group for FE-CTS to balance the skew. A better definition is skew group. This assures that the insertion delay of the group is within the skew specification.
 

In cts,clock groups can guide tool to take different clock domain skew into account,so it is only used in this stage,but optdesign have no clock group concept
 

How can we do it manually if tool doesn't optimize the skew? by using clock grouping
 

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