tjhopedream
Newbie level 2
Hi,
When switching clock domain, there is a clock glitch that propragate the clock tree in my design. Surely we can avoid such glitch by modifying the clock mux structure. But if such glitch actually happens and could not pass the timing check in simualtion($width), what effect does it cause on the silicon? Does metastability exist on the Q output of DFF in this case if the the Data input port of DFF hold stable?
When switching clock domain, there is a clock glitch that propragate the clock tree in my design. Surely we can avoid such glitch by modifying the clock mux structure. But if such glitch actually happens and could not pass the timing check in simualtion($width), what effect does it cause on the silicon? Does metastability exist on the Q output of DFF in this case if the the Data input port of DFF hold stable?