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clock gating issue with DC compiler

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kevin.memi

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Hi all,

I am working on clock gating with DC compiler tool. The problem is when setting the minbitwidth with set_clock_gating_style command. Even though I set minimum bit width is 8, when evaluate the clock gating report, I discover that there are some gating cells connect to only 2 registers ??? When I increase the bitwidth to 32 or 64, it works properly!!

Highly appreciate anyone help me.
I looking forward your response. Thank you in advance.
 

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