clock gating in flip flop

[karthikss42]

what is meant for clock gating technique applied in flip flop for reduce power consumption.i was read from net not easy to understand explain in simple..is any possible this to power consumption minimization pcb traces

 

[K-J]

what is meant for clock gating technique applied in flip flop for reduce power consumption.i was read from net not easy to understand explain in simple..is any possible this to power consumption minimization pcb traces

A flip flop does not need to be clocked with a free running clock. Clock gating is when you have some logic that then generates the clock to that flip flop as well as additional logic to generate the 'D' input to that flop.

The reason power is reduced is because it takes energy to switch any signal from one voltage level to another. By replacing a signal that is always toggling with one that only toggles when needed you are reducing the amount of energy used. Typically, clock gating can be used on printed circuit board designs and ASIC designs because in order to implement the design correctly one needs to have very good control of the minimum and maximum propogation delays. Inside an FPGA you don't have this sort of control so clock gating is not used very often...and even less often is it used successfully.

Kevin Jennings