Clock gating cells delays in post-map simulation

[alphus]

Hi all!
I have design with clock multiplexers and clock gating cells. I'm using Cadence RC compiler for synthesis. After synthesis, i need to simulate resulting netlist with SDF file using ncsim.
When i run the simulation, i see that clock MUX and gating cell delays are not '0'. How to get an SDF file with excluded clock nets, i.e. get ideal clock path through all gating cells and multiplexers?

 

[ThisIsNotSam]

most times all cells will have a unit delay. is that what you are trying to get rid of? if so, there might be a switch in the verilog file that came with the std cells. that can be used.

you can always edit the SDF by hand if that is required.

 

[alphus]

I made a Place&Route in Encounter and got netlist+SDF for simulation.
Possibly, for simulation of design with gated and multiplexed clocks needs an Clock Tree building, i.e. post-map simulation is not required..
I think, solution is place&route or verilog/sdf modification (as mentioned by ThisIsNotSam)

 

[ThisIsNotSam]

I made a Place&Route in Encounter and got netlist+SDF for simulation.
Possibly, for simulation of design with gated and multiplexed clocks needs an Clock Tree building, i.e. post-map simulation is not required..
I think, solution is place&route or verilog/sdf modification (as mentioned by ThisIsNotSam)

I have no idea what you are trying to achieve. For precise timing analysis, you can export a spice netlist directly from encounter. You can include the clock tree in it or remove it, it's an option contained in the software. There is no other way that is more precise than this. Spice is the way to go.