Clock gating cell constraints in design compiler

[kyonglee]

I have clock gating cells from a standard cell library in my RTL design, and synthesize it using design compiler.
Does design compiler automatically relates the input/output clock relationship of the clock gating cells? Or, do I manually specify clk constraints (e.g., create_generated_clock)?

Thank you in advance.

 

[tariq786]

if you have clock gating cells from the standard library. Could you post how do they look like? Please paste the code.

I am wondering do you need to synthesize these cells or not? You can avoid synthesizing these cells by putting

//translate off

before the code

and

//translate on

after the code that you dont want to synthesize. Google for more help