ivlsi
Advanced Member level 3
Hi All,
Please see below the tree structures of the Clock Gaters in FPGA.
There is a PLL, several Center Gaters (controlled by SW), and many hierarchies with local Clock Gaters, which are controlled by Internal Logic.
The problem is so that the lines, which are shown in RED, take a lot of routing resources. The Global Lines could not be taken in account since they are used for another purposes.
So, what's the solution in order to reduce the routing resources? Keeping two hierarchies for clock gating is MUST(the first hierarchy is for SW Clock Control, the second hierarchy is for Logic Clock Control).
Thank you!
Please see below the tree structures of the Clock Gaters in FPGA.
There is a PLL, several Center Gaters (controlled by SW), and many hierarchies with local Clock Gaters, which are controlled by Internal Logic.
The problem is so that the lines, which are shown in RED, take a lot of routing resources. The Global Lines could not be taken in account since they are used for another purposes.
So, what's the solution in order to reduce the routing resources? Keeping two hierarchies for clock gating is MUST(the first hierarchy is for SW Clock Control, the second hierarchy is for Logic Clock Control).
Thank you!