I have done little ASIC work, and no prototyping, but the ASIC I did work on clock gating was frowned upon and not allowed. I know it is pervasive in ASIC design though. We mostly stuck to standard FPGA style coding for the main logic, but there may have been gating in the peripherals I was not involved in. But 1000 gated clocks seems rather excessive. Are you trying to individually turn on and off 1000 modules? why so many?
Is this company work or hobby project? If for a company, dont you have someone with the correct expertise? I know there are techniques for converting gated clocks in FPGAs from reading posts at Altera and Xilinx forums - but thats the best I can do.