clock frequency after floor planning and placement

[farzian]

Hi
I synthesize a HDL code and have a clock frequency after synthesis. my question is: Does clock frequency changes after placement and floor planning? in other word, does placement and floor planning affect clock frequency?
thanks
farzian

 

[sharath666]

Your clock frequency is something that has to be decided at the beginning of the design stage based on your system/IP/throughput requirements. Once your HDL code is written, all the steps you undertake till you get a GDSII/Bitfile is oriented towards meeting this frequency.
But there may be case where the design team will be sure that they will not be able to satisfy the required clock frequency. In that case, they will have to settle for a lower frequency.
I think the question you wanted to ask is about "timing margins" and not about "clock frequency". The answer is that timing margins are affected by placement and floorplanning and they do get poorer as you proceed in the design phase.

 

[rca]

to complete the sharath666 response.
to force the synthesis to select the best structure for a certain speed (timing), you could increased the clock frequency target during the synthesis and reduce it during the PnR phases (placement, cts-....)

 

[sivateja.m]

No, but change in your clock frequency affects placement and routing.