When I wanted to have a value latched in a module, I have always done:
Code:
module my_module(clk, myinput);
input wire clk;
input wire myinput;
reg latch_myinput;
always @(posedge clk)
begin
latch_myinput = myinput;
end
endmodule
With the above code, it is clear that the input is latched synchronously to the clock clk.
An other way to latch an input is to declare myinput as "input reg":
Have you tried compiling your second method ... I use modelsim and no it does not compile and gives port mode incompatible with declaration ... which is rightly so !
My understanding of declaring a port as wire or reg is very simple ... if you are going to assign a value in initial / always block use reg else use wire .
No Input can ever be assinged so no point in declaring that as a reg it is always wire .
Synthesis tool has very little concern with reg/wire .. it is bascially more helpful to the simualtor . If you disagree with me please do mail me back