tv123
Junior Member level 3
Can anybody help me design a clock fail detection cicuits without using delay lines.
I came across the attached circuit which can detect the clock failure of a high frequency clock used as clock1 with the help of a good low frequency clock named clock2.
My doubt is whether i can detect the failure of the low frequency clock with the help of a good high frequency clock?
I have attached waveform of the below circuit and my requirement is the reverse.
Pls help
![cf.png cf.png](https://www.edaboard.com/data/attachments/53/53515-7eb933d20ff139fe5efe3f06ca4e5fd9.jpg)
![new2.png new2.png](https://www.edaboard.com/data/attachments/53/53516-b66c7ad0db455b64cfb540a09b54f695.jpg)
I came across the attached circuit which can detect the clock failure of a high frequency clock used as clock1 with the help of a good low frequency clock named clock2.
My doubt is whether i can detect the failure of the low frequency clock with the help of a good high frequency clock?
I have attached waveform of the below circuit and my requirement is the reverse.
Pls help
![cf.png cf.png](https://www.edaboard.com/data/attachments/53/53515-7eb933d20ff139fe5efe3f06ca4e5fd9.jpg)
![new2.png new2.png](https://www.edaboard.com/data/attachments/53/53516-b66c7ad0db455b64cfb540a09b54f695.jpg)