Sorry for not having a proper answer, but this is all I could get from he net :
My guess would be that this is caused by a latch based design.
I guess that a structure as the one below might cause non
50% duty-cycle clocks to be more optimal although I don't have
any personal experience in designing such latch based designs:
Logic (with delay t)
|
V
Latch (Enabled by positive clk)
|
V
Logic (with delay 2*t)
|
V
Latch (Enabled by negative clk)