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# Clock domain Synchronizers

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#### Ashish Agrawal

##### Member level 3
Hi All,

I have 2 modules in a design. Module 1 works on ClockA and module 2 works on ClockB.
There are 2 signals coming out from module 1 and going as input to module 2.
Since Module 2 works on different clock then module 1. So I will have to synchronize these inputs at ClockB before using them.
I want to do some AND/OR (combo) logic with these 2 inputs.
Which of the following technique should be used..
1. Synchronize these signals by using 2 separate synchronizers and then combine (Data coherency issue may come)
2. Combine the signals first and then synchronize using only 1 synchronizer(glitch may occur)

Please let me know if these are the only techniques to be used or is there any other technique.

Ashish

Hi Rahdirs,

Thanks for sharing this link. I already went through this link but was not able to figure out the solution for this problem. That's why I asked this question here in this forum.

Thanks,
Ashish

Hi All,

I have 2 modules in a design. Module 1 works on ClockA and module 2 works on ClockB.
There are 2 signals coming out from module 1 and going as input to module 2.
Since Module 2 works on different clock then module 1. So I will have to synchronize these inputs at ClockB before using them.
I want to do some AND/OR (combo) logic with these 2 inputs.
Which of the following technique should be used..
1. Synchronize these signals by using 2 separate synchronizers and then combine (Data coherency issue may come)
2. Combine the signals first and then synchronize using only 1 synchronizer(glitch may occur)

Please let me know if these are the only techniques to be used or is there any other technique.

Ashish

I would take the 2 signals from ClockA and perform the combo logic on them then pass it through another register on ClockA. That single bit synchronous output is what is used to cross clock domains.

I would take the 2 signals from ClockA and perform the combo logic on them then pass it through another register on ClockA. That single bit synchronous output is what is used to cross clock domains.

As I have mentioned in my first post that I don't have access to ClockA. So won't be able to use this solution.

If you know the approximate bit rate of Clock A, and Clock B, Can you re-create Clock A from the signal using an XOR to create a pulse for data transitions to re-sync the free-running clock or use a PLL.

then you can store the data in a dual port FIFO with dual clock and data with required integrity and buffer size.

Points: 2

### ydlm42sj

Points: 2
As I have mentioned in my first post that I don't have access to ClockA. So won't be able to use this solution.

What is the exact combinational logic equation that you will be using? Depending on the equation and the skew between the signals perhaps a solution will present itself. Also is ClockA faster or slower than ClockB and are the signals from ClockA single clock pulses or something else entirely?

Ashish Agrawal

### Ashish Agrawal

Points: 2
What is the exact combinational logic equation that you will be using? Depending on the equation and the skew between the signals perhaps a solution will present itself. Also is ClockA faster or slower than ClockB and are the signals from ClockA single clock pulses or something else entirely?

These signals triggers a FSM, so it's not easy to drive the exact combo logic equation. ClockA is slower than ClockB and signals from ClockA are not the single clock pulses. By the way thanks for giving the idea for using the combo equation and the skew between signals. I would be able to drive a solution now.

Hello Ashish,

Assuming the signals coming from clock A as control signals (say mux select,mode select, sw_register..).
First u can encode these signals to One hot encoding before feeding to the cdc in the clock B domain.Then add a decoder in clk B domain. So.So that u can avoid coherency and glitch issue.(clock A is slower that clock B)

Thanks,
MNM

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