clock domain crossing

[bibo1978]

how is appalix

1-synchronizer is used to decrease the probability of metastability not to allow it!
2-One bit is not data it is a signal if you want just sample it directly you will only have a more probability that ur circuit fail or hang or read wrong data for a longer period of time
you need to read more about the subject that's it I can't be more comprehensive sorry

 

[ASIC_intl]

clock domain crossing register fifo

Hi bibo

I have read it. Probably u need to either think of the matter more or read about more. I am sorry for this.

 

[feel_on_on]

cross clock domain fifo grey code

I also have the same problem as ASIC_intl, I don't know if the problem have been solved ? Can ASIC_intl tell me ?

 

[bibo1978]

crossing clock domains + digital design

Bottom line use Async FIFO

 

[feel_on_on]

cross clock domain synchronization double flop

if you have one bit then also you can have a metastable invalid bit when you are using two flop synchronizer instead of a FIFO. But for a single bit we do not go for a FIFO but go for a two flop synchronizer. How can you allow the illegal metastable one bit but you cannot allow illegal metastable multibit state (e.g. 0101 here)?

 

[bibo1978]

grey code in clock crossing domain

Guys,
if you read wrong data this doesn't mean metastability ... !
just simply according to any logic data should be sampled at some specific time (hold period) which is managed by passing the clock.
when you read data Bus Asynchronously you may get wrong value because you might be sampling the data on its transmittion period and there are many things that might cause wrong bus data output one of which is the wire delay is different, the Flip flop response time, clock jitter, recieving FF clock delay, sampling at invalid data value (between the logic zero and one) ... etc. The list is big here, so what you have to do is to avoid all of this one way or the other

I want to clarify metastability a bit here, it is a very small range of input that may cause circuit to hang i.e. transistor will be in active state.
just to get it more clear, a gate will definitely behave in specific manner if input voltage is within some range for example TTL will give you 0 if input is between 0-0.2 Volt. and one if input is between 3.7 and 5 (this values might be wrong values I am using it for clarification only you can search the net to get the range of TTL logic for input and output) if the data input value is between 0.2 - 3.7 the output might be 0-1 (can not determine), there is within this range avery small range that will make the circuit go to metastability (i.e. transistors will be in active state and transmit this to next output). this (range) is very small and actually is not precise because it depends on the dopping, the material type, temprature ... etc. so simply there is just a very small change that if you sample the data you might sample it with this value that might cause a circuit failure or a hang period for transistor to return from active state .. it might cause also total circuit failure ! very rarely if it propagates.
This is metastability Guys this is metastability .. nothin else.
so as long as your circuit is behaving right which means that it is working then you didn't get to metastability state.
I hope it is clear now.
Now back to our discussion you will still need a Async FIFO for Data bus and in case of one signal you might use only two FF in case you are sampling at a higher speed, you will need other techniques in case you are sampling a a lower clock speed.
hope this help

 

[feel_on_on]

8 to 16 cross clock

You mean that metastability with two DFF still is possible to cause a circuit failure ,only beacuse the range is small .When transmit a "1" to 2 DFF from a clock domain to another clock domain, Due to setup timing , circuit enter into metastability in the first DFF ,although in the seconde DFF , the data have been stable ,but now it is "0". this cause a failure.

 

[bibo1978]

how does grey code help async clock crossing

I don't understand your question however I will add a note, that might answer u, the metastability filter (two FFs usually) diminish the probability of metastability propagation, which might cause circuit failure, metastability might also cause circuit to hang .. unexpected behavior generally , more FFs will decrease metastability exponentially.. yet there are no way to have a zero propability for metastability propagation (in Async. circuits or in life) but it can be very low such that it "may" never occur during lifetime of the circuit.
Two FF difinitely will make this happen three is a plus.

 

[feel_on_on]

data bus clock domain crossing

more FFs will decrease metastability, but are you sure the correct data you got ? If you transmit a "1",but you get a "0" in the end . more FFs only can solve metastability ,but can't sure a correct data you get . ie: now transmit "1" through one FF crossing clock domain ,you get a metastability. For solving the metastability ,you add another FF,now two FFs. although you solved metastability,but you maybe get a "0" in the two FFs output.

 

[feel_on_on]

clock domain crossing synchronizer

hi,bibo1978
Can you help me ? I don't understand why the deepth is 20bit . thanks a lot .

the spec as following :

The REF_CLK frequency shall be 50Mhz+/-50ppm with a duty cycle between35% and 65% . the recovered clock is 25Mhz+/-100ppm.

While the PHY may recover clock from in the incoming data stream,the receiver shall account for the differences between the local REF_CLK and the recovered clock through use of sufficient elasticity buffering. The elasticity buffer design shall not affect the Inter-Packet Gap for received IPGs of 36 bits or greater. To tolerate the clock variations specified here for Ethernet MTUs,the elasticity buffer shall tolerate a minimum of +/-10 bits. This implies that the FIFO is at least 20bits deep and doesnot transfer recovered data on RXD[1:0] unitil FIFO is half full.

anyone can tell me how to got +/-10bit