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flop based synchronizers are suitable when number of signals crossing cock domain are limited say 2-3. when you are transferring data of 8, 16 or more bits, FIFO is more convenient & reliable way.
refer to digital design principles and practice By John Walkerly.
It has good theory on synchronizers .You can get a digital copy in ebooks section on edaboard.
when the no of signals crossing the clock domain is more that 2/3 i,e if it is 8, 16 more then you cannot use 2 flops as there is no gurantee that even if you use 8/16 flops for each bit to syncronize will be sampled correctly.
The best way if you want to use 2 flops in this case is to convert the bibary to gray code as only one bit will be changing at a time. Suppose u have like 4 bits ..
so from 0000---> 1111 there are 4 bits changing so each bit cannot be sampled with 2 flops effectively id u use 2 flops.
Secondly if there is data rate is concerned then you need a buffer mechanism so you need FIFO . 2 Flops wont do .
So for control signal we use 2 flops and in data matching and synchronizing we use FIFO ..
lets say there is an asynchronous bus A[3:0] that is being sampled by a different freq domain with double flops and the sampled output is Ax[3:0].
Lets say A[3:0] changed from 0000 to 1111 with all the bits changing around the same time. On account of the asynchronous nature of the signals, Ax[3:0] may change from 0000 to 0101 in one cycle and the next cycle 0101 changes to 1111. So, the intermediate value on Ax 0101 is illegal. Ax should have changed from 0000 to 1111 without any intermediate illegal value.
So, when we have a bus, we use a FIFO. If it is a single control signal, there is no case of illegal intermediate state since there are only two states.
Suppose there is a one bit that is being synchronized by two flops. Suppose in first clock domain it is logic high. Now when it enters new clock domain due to metastability it may not be properly trnsferred and appeared as an erroneous value of logic zero as an intermediate state. So in the way your 4 bit bus prduces an illegal state 0101, here in a similar way in new clock domain we get appearance of an illegal state of logic zero instead of the logic 1. Now after some time it will go to its propoer state of logic one in the same way as your 0101 state will reach the legal state 1111.
FIFO is used when you need to transfer data from one clock domain (clock domain at which you store data) to another clock domain, it grantees that the data will cross from that domain to the other (smoothly) if the Asynchronous FIFO is designed right (Async FIFO usually will include Synchronizers or similar approaches) FIFO will introduce latency to assure that the data crosses the domain approriately
The syncronizer on the other hand is a way to avoid metastability that can be caused by sampling an asynchronous "in a slower clock" (signal) to another time domain (faster), the synchronizer is a way to avoid sampling at intermediate state of a signal which can cause metastability it only decrease the proabability of metastability (there is a mathematical theory behind this I think it is called Burden thoery) so if you add more FFs to synchronizer you propably can sample a signal with less probpility of trapping into some intermediate state, for instance with three flips you get an even lower probability, there is no grantee that if you sample a bus using synchronizers you will get the actual value so synchronizers are only for metastability problem, that's because you can sample a signal with a synchronizer (or more) but you can get the value a data bus with a synchronizer because you don't know for sure that when you are sampling each synchronizer is sampling the data bus on its valid state (after setup time and before transit time)
The concept is totally different (to read a data) you need to know when you are sampling it (FIFO do this because it uses the first clock domain to register the Data and hold it valid until it is read), internally the FIFO will send a cross signal to its counters which will run asynchronously (so you can't use a simple binary counter in FIFO, usually you need a grey counter or another complex counter that can't have multiple transit of bits. Async FIFO design can be very tricky
In my example, I am assuming that by using a double flop, the probability of failure due to metasatibility is very little. Therefore, the sampled output has proper logic levels. If the probability of failure is still high, you may need to add more flops in the synchronizer until the probability of failure is acceptable for the specific design. When there is metastability in the first flop, the probability of metastability in the second flop is greatly reduced and so on.
In the example that I had, if A changes from 0000 to 1111 at the same time as the sampling clock rises, there could very well be metastability in the first synchronizer flops. And when the second synchronizer flop samples the output of the first flop, it may see values 0101 (for example) due to the metastability in the first flop. However, by the second sampling cycle at the first flop, the input data would have stabilized and it would see perfect 1111. So, ultimately Ax will be 1111 but with intermediate illegal logic state.
In your example u have an intermediate illegal state 0101 of four bits. Let us take your MSB (left most bit) out of these four bits. Due to metastability it is getting an illegal intermediate vaue of zero rather than legal value of high. So this is also problemful for one bit. I want to say this only in my last reply. Do u understand now? Comment on this.
In your example u have an intermediate illegal state 0101 of four bits. Let us take your MSB (left most bit) out of these four bits. Due to metastability it is getting an illegal intermediate vaue of zero rather than legal value of high. So this is also problemful for one bit. I want to say this only in my last reply. Do u understand now? Comment on this.
Hi Asic_intl,
If we consider only the MSB in my example, there is no logic problem, only latency problem. If we were monitoring only the MSB in the sampling domain, we will observe the transition from '0' to '1' one cycle late in the event of metastability.
The logic on the sampling side will just assume that the asynchronous input just came late.
In the case of the bus Ax[3:0]:
Ax (w/o metastability) : 0000 -> 1111 -> 1111
Ax (w metastability on bits 3 & 1) : 0000 -> 0101 -> 1111
If we are monitoring Ax[3:0] we expect them to be coherent as they transition from one freq domain to the next. In the example above, bits 3 and 1 had metastability and ended up as '0' while bits 2 and 0 either did not have metastability or did have metastability but ended up as '1'. The sampling side logic sees 0101 on bus Ax which it should not have.
Basically, when we are crossing frequency domains, a hit on latency is acceptable but lack of coherency in the data bits is not acceptable.
guys metastability is not that you read wrong data it is that your circuit might work in non descrete mode simply your FF is more or less some transistors they are designed in such a way that it will usually be saturated or switched off (on-off) however there is some input signal that might inteosice invalid input let's say in TTL a zero is between 0-0.2 v and one is between 4.7 and 5.2 v an input below 1.4v is considered a zero and an input above 2.4 is considered a one anyway this circuit is still an analog circuit at some voltage this circuit will produce some signal blbetween the 0.2 and 4.7 and it may hang because the transistors might be in active state ( not saturated or switched off),it might stay there for a while, to note that this input exactly will differ from a gate to another ,that's the metastability it is state of inaccuracy of output and it is meta stable. This concept is mathematically valid for a lot of issues when you try to make a descrete result from a non descrete input it has some probability and it might happen to you in life when you are in some critical descision let's say u are in a railway of a train that by accident you just passed the train gate and it closes and now you have to decide what to do go forward or backward u might hang on there for a while thinking
that's metastability it is not only violation of setup time only it is less than this
let's say u are in a railway of a train that by accident you just passed the train gate and it closes and now you have to decide what to do go forward or backward u might hang on there for a while thinking
Metastable means exactly what it says, "meta"-"stable".
If you were to look at the butterfly curve for the feedback path of a latch, it has two stable points (vdd,0) and (0,vdd) and one metastable point close to (vdd/2, vdd/2) depending on how the latch is sized. When the latch closes before the internal nodes had a chance to reach from (vdd,0) to (0,vdd) or vice versa, you may be stuck in the middle (Vx, Vy). If this is very close to the metastable point, you will be stuck for a long time there before resolving to (0,vdd) or (vdd,0) which ever is closer. The farther away from the metastable point and closer to one of the stable points you are when the latch closed, the faster you will resolve to the closest stable point ( or the closest gate as in the above example).
Why will not the coherency in the databit be acceptable?
There will be a metstable state of 0101 in your case. But after a latency you will get the correct state of 1111 which will be sampled to the new clock domain. What problem will this erroneous state of 0101 will create?
Now if 0101 crates a problem as a metastable state. Then for a single bit also the intermediate metastable single bit state will create the same problem.
Added after 3 minutes:
Hi apallix
Why will not the coherency in the databit be acceptable?
There will be a metstable state of 0101 in your case. But after a latency you will get the correct state of 1111 which will be sampled to the new clock domain. What problem will this erroneous state of 0101 will create?
Now if 0101 crates a problem as a metastable state. Then for a single bit also the intermediate metastable single bit state will create the same problem.
Added after 13 minutes:
HI kvingle
Where in wakerely they have described about synchronization of a data bus like 8 bit and 16 bit?
0101 is not a metastable state, when you read 0101 usually means that data was read on its transition state but since you read some value then you read right the problem mainly is that value that you didn't reach metastable state.
If you read data bus async you may get fake value I.e value that is not what it is in its clock domain because simply a clock domain defines exactly when data must be read by the clock itself
That's why why u will need an Async FIFO to transmit data from one domain to the other
because from one side the FIFO is capable to read data right and from the other side it will deliver it right I.e it will simply hold data until it is valid to be read from the other side
for example imagine two two group of water people that are transferring balls between them on group is doing this with some defined timing such that anyone in this group will try to get the ball at some very small period of time if he rounds a ball then it is one else is zero each member of this group is authorized to prepare the passed ball to the next member in some definite time such that when the other member try to get the ball it is valid the other group is doing the same but with another rate now interfacing the two groups directly will be a mess we need some group in the middle that knows can get the balls from one clock and then send it to the other this group job is not easy they might need to hold the balls for some time until it is valid to be read on the other clock domain
I understand what u have written. But instead of four bits if you have one bit then also you can have a metastable invalid bit when you are using two flop synchronizer instead of a FIFO. But for a single bit we do not go for a FIFO but go for a two flop synchronizer. How can you allow the illegal metastable one bit but you cannot allow illegal metastable multibit state (e.g. 0101 here)?
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