There are many issues with clock domain crossing.
In asynchronous designs you need to be worried about setup/hold time violations as well as metastability.
If you are switching between two clocks (i.e. two clocks muxed or clock gating) you need to be worried about glitches in the clock.
If you are talking about clock dividers or multipliers, again setup and hold time violations become an issue.
A good synthesis tool with the proper constraints can check most of these, the difficult constraints however involve asynchronous clock signals.
It is also very important to think about potential clock switching problems when designing. You need to consider things like early and late clock arrival and the relationship between your clocks.
It would be easier to help if you provided a little more insight into your problem, I am hoping this sets you on the correct path though.