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clock domain crossing verification

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tariq786

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Hi

I am curious to know how would you find bugs in clock domain crossing paths by simulation?
Are there any other alternatives to simulation?
Are there any corner case bugs?
How to define coverage of clock domain crossing paths?


You input will be really appreciated
 

GiuseppeLaPiana

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There are many issues with clock domain crossing.
In asynchronous designs you need to be worried about setup/hold time violations as well as metastability.
If you are switching between two clocks (i.e. two clocks muxed or clock gating) you need to be worried about glitches in the clock.
If you are talking about clock dividers or multipliers, again setup and hold time violations become an issue.

A good synthesis tool with the proper constraints can check most of these, the difficult constraints however involve asynchronous clock signals.
It is also very important to think about potential clock switching problems when designing. You need to consider things like early and late clock arrival and the relationship between your clocks.

It would be easier to help if you provided a little more insight into your problem, I am hoping this sets you on the correct path though.
 

dftrtl

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Run CDC spyglass for this. It is very hard to catch these things in simulations
 

sakthikumaran87

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0-in CDC from Mentor is a product particularly to catch CDC bugs and its really efficient.
 

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