Clock domain crossing timing error

[s3034585]

false path clock domain

hi Guys
In my design there are 2 clks called as fastclk and slwclk and they are generated using DCM. I am using a signal which is from slwclk domain to trigger a state machine in fast clk. But before using it i do synchronise it using 2 ffs clocked by fast clk. Still i am getting some timing errors and i an unable to understand it. Can any one help me understand it..

Thanks in advance
tama

the error is ---->

Slack: -1.899ns (requirement - (data path - clock path skew + uncertainty))
Source: gen_coproc.i_copro_top/g1.0.si_c/i_vg_gray/dvwr_dn (FF)
Destination: gen_coproc.i_copro_top/g1.0.si_c/i_vg_gray/dvwrdn_r (FF)
Requirement: 0.003ns
Data Path Delay: 1.902ns (Levels of Logic = 0)
Clock Path Skew: 0.000ns
Source Clock: slow_clk rising at 110135.805ns
Destination Clock: fast_clk rising at 110135.808ns
Clock Uncertainty: 0.000ns

Data Path: gen_coproc.i_copro_top/g1.0.si_c/i_vg_gray/dvwr_dn to gen_coproc.i_copro_top/g1.0.si_c/i_vg_gray/dvwrdn_r
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X86Y145.YQ Tcko 0.568 gen_coproc.i_copro_top/g1.0.si_c/i_vg_gray/transation_done
gen_coproc.i_copro_top/g1.0.si_c/i_vg_gray/dvwr_dn
SLICE_X86Y144.BY net (fanout=1) 0.964 gen_coproc.i_copro_top/g1.0.si_c/i_vg_gray/dvwr_dn
SLICE_X86Y144.CLK Tdick 0.370 gen_coproc.i_copro_top/g1.0.si_c/i_vg_gray/dvwrdn_r
gen_coproc.i_copro_top/g1.0.si_c/i_vg_gray/dvwrdn_r
------------------------------------------------- ---------------------------
Total 1.902ns (0.938ns logic, 0.964ns route)
(49.3% logic, 50.7% route)

--------------------------------------------------------------------------------

 

[benradu]

clock domain crossing false paths

It depends how you do the synchronization. Ideally you should generate a pulse with the same width as the fastclk period and use it to trigger your state machine.
Also, from your post I see the 50.7% of delays is from routing and this can be improved if you play with the MAP an PAR settings. Increase the routing effort, use timing driven mapping...

 

[anmolvlsi13]

synchronization false path timing

Use more FF instead of 2 to synchronize the clk as increases the FFreduce the Probability of Metastabilty.

Anmol

 

[Aastik]

Hi,

I think you are getting the slack (error) because the source clock and the destination clock are different. when source clock and destination clock are different along a path the tool is supposed to give timing voilations for that path. since you are using 2 FFs for synchronization, that should work fine and you can simply ignore the timing voilation. For such cases, It is recommended to give TIG (Timing Ignore) constraint between the two clock domains. If you give TIG between your fastclk and slowclk, this timing voilation will not be reported in twr.

Thanks.

 

[gold_kiss]

You need to define false path for signal crossing from one domain to another.

 

[Alfred_zhang]

in your ucf, use
TIMESPEC "TS_XXX" = FROM "slow_clk" TO "fast_clk" TIG;

maybe helpful.

 

[avimit]

When corrsing clock domains, you will always get a timing error. It is perfectly fine. because you will have timing violations in silicon as well. Now there are two ways to tackle it:
1. Just ignore it
2. Declare a false path(s) between two clock domains.
Kr,
Avi
http://www.vlsiip.com

 

[nag123]

What is false path and how to declare that one?

 

[avimit]

A false path is a timing path which is never sensitized in reality, but does exists in the chip. Since STA tool cannot find it, and its only the engineer who knows its a false path, it may be possible that STA reports a timing violation, and actually an engineers knows that this violation isn't true.

But in this case the path from one clock domain to another is not a 'true false path' as it WILL be sensitised on chip. But since we know that there would be timing viols and we have put measures in place so that our silicon does work despite of that, we use the 'false path' utility to declare it a 'false path' so that STA does not produce timing errors:
In design complier you can declare a false path like this:
set_false_path -from Clk1 -to Clk2
other examples may be seen at
http://www.vlsiip.com/dc_shell or you may want to see the man page of 'set_false_path'
Any more questions? let me know and I will try to clarify.
Kr,
Aviral Mittal