s3034585
Full Member level 4
false path clock domain
hi Guys
In my design there are 2 clks called as fastclk and slwclk and they are generated using DCM. I am using a signal which is from slwclk domain to trigger a state machine in fast clk. But before using it i do synchronise it using 2 ffs clocked by fast clk. Still i am getting some timing errors and i an unable to understand it. Can any one help me understand it..
Thanks in advance
tama
the error is ---->
Slack: -1.899ns (requirement - (data path - clock path skew + uncertainty))
Source: gen_coproc.i_copro_top/g1.0.si_c/i_vg_gray/dvwr_dn (FF)
Destination: gen_coproc.i_copro_top/g1.0.si_c/i_vg_gray/dvwrdn_r (FF)
Requirement: 0.003ns
Data Path Delay: 1.902ns (Levels of Logic = 0)
Clock Path Skew: 0.000ns
Source Clock: slow_clk rising at 110135.805ns
Destination Clock: fast_clk rising at 110135.808ns
Clock Uncertainty: 0.000ns
Data Path: gen_coproc.i_copro_top/g1.0.si_c/i_vg_gray/dvwr_dn to gen_coproc.i_copro_top/g1.0.si_c/i_vg_gray/dvwrdn_r
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X86Y145.YQ Tcko 0.568 gen_coproc.i_copro_top/g1.0.si_c/i_vg_gray/transation_done
gen_coproc.i_copro_top/g1.0.si_c/i_vg_gray/dvwr_dn
SLICE_X86Y144.BY net (fanout=1) 0.964 gen_coproc.i_copro_top/g1.0.si_c/i_vg_gray/dvwr_dn
SLICE_X86Y144.CLK Tdick 0.370 gen_coproc.i_copro_top/g1.0.si_c/i_vg_gray/dvwrdn_r
gen_coproc.i_copro_top/g1.0.si_c/i_vg_gray/dvwrdn_r
------------------------------------------------- ---------------------------
Total 1.902ns (0.938ns logic, 0.964ns route)
(49.3% logic, 50.7% route)
--------------------------------------------------------------------------------
hi Guys
In my design there are 2 clks called as fastclk and slwclk and they are generated using DCM. I am using a signal which is from slwclk domain to trigger a state machine in fast clk. But before using it i do synchronise it using 2 ffs clocked by fast clk. Still i am getting some timing errors and i an unable to understand it. Can any one help me understand it..
Thanks in advance
tama
the error is ---->
Slack: -1.899ns (requirement - (data path - clock path skew + uncertainty))
Source: gen_coproc.i_copro_top/g1.0.si_c/i_vg_gray/dvwr_dn (FF)
Destination: gen_coproc.i_copro_top/g1.0.si_c/i_vg_gray/dvwrdn_r (FF)
Requirement: 0.003ns
Data Path Delay: 1.902ns (Levels of Logic = 0)
Clock Path Skew: 0.000ns
Source Clock: slow_clk rising at 110135.805ns
Destination Clock: fast_clk rising at 110135.808ns
Clock Uncertainty: 0.000ns
Data Path: gen_coproc.i_copro_top/g1.0.si_c/i_vg_gray/dvwr_dn to gen_coproc.i_copro_top/g1.0.si_c/i_vg_gray/dvwrdn_r
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X86Y145.YQ Tcko 0.568 gen_coproc.i_copro_top/g1.0.si_c/i_vg_gray/transation_done
gen_coproc.i_copro_top/g1.0.si_c/i_vg_gray/dvwr_dn
SLICE_X86Y144.BY net (fanout=1) 0.964 gen_coproc.i_copro_top/g1.0.si_c/i_vg_gray/dvwr_dn
SLICE_X86Y144.CLK Tdick 0.370 gen_coproc.i_copro_top/g1.0.si_c/i_vg_gray/dvwrdn_r
gen_coproc.i_copro_top/g1.0.si_c/i_vg_gray/dvwrdn_r
------------------------------------------------- ---------------------------
Total 1.902ns (0.938ns logic, 0.964ns route)
(49.3% logic, 50.7% route)
--------------------------------------------------------------------------------