Clock domain crossing problem

[adivy]

Hi,
I am using a gated clock A domain(outside the FPGA) to send data to a clock B domain in FPGA where clock A is slower than clock B.
Here to synchronize the data transmission I have used an asynchronous FIFO .
FIFO write clock is CLKA(generated inside the FPGA and equal to 3*clock A) as FIFO requires continuous clock.
Still the data is not written correctly i.e sometimes fifo writes extra data.
Can anyone help me out on the same?

 

[TrickyDicky]

why not just use clock A?
THe problem is probably a code bug. Have you written a testbench?

 

[adivy]

I read in FIFO datasheet that it needs a continuous clock.So gated clock can't be given directly as input.
Yes I have written test bench and it is in TB I am getting this problem.

 

[barry]

I think your write clock HAS to be synchronous with your input data, that's not what you've done by using your internal clock.

You should look into either:

1) a FIFO that doesn't need a continuous write clock
2) generating a continuous clock on the write side
3) using a different synchronizer